View HMC700LP4_8889069.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 1 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll features functional diagram ? 8 ghz, 16 bit prescaler ? fractional or i nt eger modes ? ultra low phase n oi se 6 ghz; 50 mhz r ef . -103 / -108 dbc/hz @ 20 khz (frac / i nt eger) figure of merit (f o m) -2 21 / -226 dbc/hz (frac / i nt eger) ? 24 bit step size resolution, 3 hz typ ? 200 mhz, 14bit reference path input ? direct fsk modulation mode ? c yc le slip prevention ? r ea d / write serial port, c hi p i d ? 24 l ead 4x4mm sm t p ackage: 16mm2 typical applications ? base stations for mobile r ad io ? wim a x ? t es t & measurement ? ca t v eq uipment ? phased a rr ay a pp lications ? simple fsk links ? dds r ep lacement information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 2 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll electrical specifcations, vddcp, vcccp = 5v; rvdd, avdd, dvddm, vddpfd, dvdd, vddio, dvddq, vccps, avcc = 3.3v 5%; agnd = dgnd = 0v parameter c on ditions min t yp max units rf input characteristics max r f i nput frequency ( 3.3v) 8 9 ghz min r f i nput frequency 1 00 200 mhz r f i nput sensitivity ac c oupling only. r ec ommended range -10 to -5dbm. o pe ration with higher levels, up to +7dbm is allow- able, but phase noise degradation may occur. -10 0 dbm r f i nput level differential ac coupling only. - 16 +6 dbm 16 bit divider ( i nteger) n divide ratio, 2 16 + 31 32 65,567 16 bit divider (fractional) 2 16 -1 36 65,535 ref input characteristics max r ef i nput frequency ( 3.3v) 200 mhz min r ef i nput frequency 2 00 khz r ef i nput sensitivity ac coupling only. r ec ommended level >500mvpp. with 250mvpp phase noise degradation may occur. 250 3000 mvpp r ef i nput level differential ac c oupling only 250 5000 mvpp 14 bit r ef divider r ange 1 1 6,383 phase detector phase detector frequency (frac) 50 70 mhz phase detector frequency ( i nt eg) 0.2 100 mhz general description t he hm c 700lp4(e) is a sige bi c m o s fr actional- n pll. t he pll includes a very low noise digital phase frequency detector (pfd), and a precision controlled charge pump. t he fractional pll features an advanced delta-sigma modulator design that allows both ultra-fne step sizes and very low spurious products. spurious outputs are low enough to eliminate the need for costly direct digital synthesis (dds) references in many applications. t he hm c 70 0lp4(e) phase-frequency detector (pfd) features cycle slip prevention ( c sp ) technology that allows faster frequency hopping times. ultra low in-close phase noise and low spurious also permit architectures with wider loop bandwidths for faster frequency hopping and low micro-phonics. fsk mode allows the synthesizer to be used as a simple low cost direct fm transmitter source. r ecommended level >500mvpp. with 250mvpp phase noise degradation may occur. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 3 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll absolute maximum ratings n ominal 3v supplies to g n d -0 .3v to +3.6v n om inal 3v digital supply to 3v a na log supply -0.3v to +0.3v n om inal 5v supply to g n d -0 .3v to +5.8v v co d ivider i np ut single-ended +7 dbm v co d ivide i np ut differential +13 dbm maximum junction t em perature +125 c c on tinuous power diss. ( t = 85 c ) (de rate 51 mw/ c a bove 85 c 3. 3 w t he rmal r es istance ( r 1) ( junction to ground paddle) 19.7 c /w r ef ow soldering peak t em perature t im e at peak t em perature 260 c 40 s ec o pe rating t em perature -40 c t o +85 c st orage t em perature r an ge -65 c t o +125 c es d sensitivity (hbm) c la ss 1b stresses above those listed under a bs olute maximum r at ings may cause permanent damage to the device. t hi s is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical specifcations, vddcp, vcccp = 5v; rvdd, avdd, dvddm, vddpfd, dvdd, vddio, dvddq, vccps, avcc = 3.3v 5%; agnd = dgnd = 0v parameter c on ditions min t yp max units charge pump max o utput c urrent 2 m a min o utput c urrent 5 00 a c harge pump n oise i nput referred, 50 mhz ref, 2 0 khz -145 dbc/hz logic inputs v i h i nput high voltage v dd io -0 .4 vdd io v v i l i nput l ow voltage 0 0.4 v logic outputs v o h i nput high voltage v dd io -0 .4 vdd io v v o l i nput l ow voltage 0 0.4 v serial port max c lo ck 50 mhz power supplies r vdd, a vdd, vddpfd, a v cc , v cc ps - a nalog suppl y a vdd should equal dvdd 2 .7 3.3 3.4 v dvdd, dvddm, dvddq, vdd io C digit al supply a ll must be equal 2 .7 3.3 3.4 v vdd c p , v ccc p c har ge pump supplies v ccc p a nd vdd c p must be equal 4.5 5 5.5 v t otal c urr ent c onsumption (5v) 6 ghz operation 5. 5 7 m a t otal c urr ent c onsumption (3v) 6 ghz operation 90 1 10 m a po wer down c urr ent 1 10 a bi as reference voltage measured with 10 g o hm meter 1.880 1.920 1.960 v phase noise 6 ghz v co , i nt eger mode 20khz offset, 50 mhz fpfd -108 dbc/hz 6 ghz v co , fr actional mode 20khz offset, 50 mhz fpfd -103 dbc/hz information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 4 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll pin n umber f unction description 1 s c k se rial port clock input 2 sd i se rial port data input 3 dvdd power supply pin for internal digital circuitry. n om inally 3v 4 vdd io po wer supply for digital i / o d river 5 ld_sd o lo ck detect, main serial data o ut put or v co s erial port data o ut 6 d 0 gp o o ut put bit 0, v co s erial port le when in v co s erial port mode 7 d1 gp o o ut put bit 1, v co s erial port c lo ck when in v co s erial port mode 8 dvddm digital power supply for m- c ou nter, n om inally 3v 9 v cc ps a na log power supply for prescaler, n om inally 3v 10 r f i p i np ut to the r f pr escaler. t hi s small signal input is ac-coupled to the external v co . 11 r f in c om plementary i np ut to the r f pr escaler. for single-ended input this point must be decoupled to the ground plane with a ceramic bypass capacitor, typically 100 pf. 12 a v cc a na log power supply pin for the r f se ction. a d ecoupling capacitor to the ground plane should be placed as close as possible to this pin. n om inally 3v 13 vdd c p +5 v power supply for charge pump digital section 14 v cc c p +5 v power supply for the charge pump analog section 15 c p c ha rge pump output 16 vddpfd a na log power supply for the phase frequency detector, n om inally 3v 17 b ia s [1] external bypass decoupling for precision bias circuits, 1.920v 20 mv [1] 18 a vd d a na log power supply for analog ref paths, n om inally 3v 19 r ef n r ef erence input ( n eg ative or decoupled) 20 r ef p r ef erence input (positive) 21 r vd d r ef p ath supply 22 dvddq digital supply for substrate, n om inally 3v 23 c e c hi p enable 24 se n se rial port latch enable input [1] n ot e: b ia s re f voltage cannot drive an external load. must be measured with 10g o hm m eter such as a gi lent 34410 a , ty pical 10mohm dvm will read erroneously. pin descriptions information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 5 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll figure 1. typical phase noise plots figure 2. comparison of low pfd integer mode w/ high pfd fractional at 1 ghz figure 3. typical phase noise performance vs. charge pump output voltage figure 4. rf divider sensitivity vs. frequency, mode and temperature, +3.3v figure 5. example of cycle slip prevention for frequency hop from 5200 to 3950 mhz figure 6. typical reference sensitivity vs. frequency, 3.3v -170 -160 -150 -140 -130 -120 -110 -100 -90 10 3 10 4 10 5 10 6 10 7 10 8 all plots 50 mhz pfd frequency offset (hz) 5800 mhz integer 5801 mhz fractional 2901 mhz fractional 2900 mhz integer 725 mhz fractional phase noise (dbc/hz) -50 -40 -30 -20 -10 0 10 20 0 50 100 150 200 250 300 frequency (mhz) r = max, +25c r = 3, +85c r = max, +85c r = 3, +25c sensitivity (dbm) 3900 4100 4300 4500 4700 4900 5100 5300 -10 0 10 20 30 40 50 60 70 time (usec) csp on csp off frequency (mhz) -40 -30 -20 -10 0 10 20 0 2000 4000 6000 8000 10000 frequency (mhz) integer fractional +25c +85c fractional integer sensitivity (dbm) -110 -105 -100 -95 -90 -85 -80 0 1 2 3 4 5 6 3800 4200 4600 5000 5400 tuning voltage (v) frequency (mhz) phase noise tuning voltage phase noise (dbc/hz) -170 -150 -130 -110 -90 -70 10 2 10 3 10 4 10 5 10 6 10 7 10 8 frequency offset (hz) -99.5dbc, 1ghz, 200khz pfd = -226.4dbc fom fractional mode 25mhz pfd integer mode 200khz pfd -107dbc, 1ghz, 25mhz pfd = -213dbc fom phase noise (dbc/hz) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 6 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll theory of operation t he hm c 700lp4(e) is targeted for ultra low phase noise applications. t he synthesizer has been designed with very low noise reference path, phase detector and charge pump. external vco t he hm c 700lp4(e) is targeted for ultra low phase noise applications with an external v co . t he synthesizer charge pump can operate with the charge pump supply as high as 5.5 volts. t he charge pump output at the varactor tuning port, normally can maintain low noise performance to within 500mv of either ground or the upper supply voltage (see example ( fgure 3 ) figure 7. HMC700LP4(e) synthesizer with external vco high performance low spurious operation t he hm c 700lp4(e) has been designed for the best phase noise possible in an integrated synthesizer. spurious s ignals in a synthesizer can occur in any mode of operation and can come from a number of sources. i n g eneral spurious can be the result of interference that gets through the loop flter and modulates the input tuning port of the v co directly. i t c an also result from interference that modulates the v co indirectly through power supplies, ground, or output ports, or bypasses the loop flter due to poor isolation of the flter. i t c an also simply add to the output of the synthesizer. i nt erference is always present at multiples of the pfd frequency, and the input reference frequency. depending upon the mode of operation of the synthesizer spurious may also occur at integer sub-multiples of the reference frequency. i f t he fractional mode of operation is used the difference between the v co frequency and the nearest harmonic of the reference, will also create what are referred to as integer boundary spurs. t he synthesizer necessarily contains digital circuitry to control the prescaler. t he circuitry mostly operates at the pfd frequency. t he re is more circuitry active in fractional mode, hence more full switching c m o s i s used and the potential for interference is greater. t he hm c 70 0lp4(e) has been designed and tested for low spurious performance in either integer or fractional mode of operation. r ef erence spurious levels are typically below -100 dbc, and in-band fractional boundary spurious are typically below integrated phase noise, frequency planning can improve spurious performance in many cases. r efer ence spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the v co from the digital switching of the synthesizer, isolation of the v co load from the synthesizer and isolation of the crystal from the v co . t ypical boar d layout, evaluation boards and application information are available for low spurious operation. o per ation with lower levels of isolation in the application circuit board from those recommended by hittite may result in higher spurious levels. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 7 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll reference input stage t he reference input provides the path from the external reference source to the phase detector. t he input stage of the reference path is shown in figure 8. hm c 70 0lp4(e) is a d c coupled, common emitter differential n p n buffer. i np ut pins have 1.8v bias on them. expected input is full swing 3v c m o s. slightly degraded phase noise performance may result with quasi sine or sine inputs. i np ut reference should have a noise foor better than -155 dbc/hz at 50mhz to avoid degradation of the input reference path. t he input reference path phase noise foor is approximately equivalent to -155 dbc/hz. t hi s input should be well isolated from the v co f or best spurious performance in fractional mode. figure 8. reference path input stage ref path r divider t he reference path r d ivider is based on a 14 bit counter and can divide input signals of up to 220 mhz input by values from 1 to 16,383 and is controlled by rdiv ( t ab le 9 ). rf input stage t he r f input stage provides the path from the external v co to the phase detector via the fractional divider. t he r f in put path is rated to operate nominally from 100 mhz to 8 ghz. t he hm c 70 0lp4(e) r f i nput stage is a differential common emitter stage with d c coupling, and is protected by esd diodes as shown in figure 9. t he r f i np ut stage is internally matched from a single ended 50 ohm source above about 3.5 ghz, with the complimentary input grounded. i f a be tter match is required at low frequency a simple shunt 50ohm resistor can be used external to the package. t he r f i nput stage has excellent sensitivity (see fgure 4). excessive drive levels can result in more coupling and spurious products in fractional mode. -10 dbm is a recommended drive level. figure 9. rf input stage information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 8 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll rf path n divider t he main r f p ath divider is capable of average divide ratios between 2 16 -1 (65,535) and 36 in fractional mode, and 2 16 + 31 (65,567) to 32 in integer mode. charge pump and phase frequency detector t he phase frequency detector or pfd has two inputs, one from the reference path divider and one from the r f p ath divider. when in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. we refer to the frequency of operation of the pfd as ? pfd . most formula related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the pfd, ? pfd . t he pfd c ompares the phase of the r f p ath signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. t he output current varies linearly over a full 2 radians input phase difference. pfd test functions phase detector registers are mainly used in test. pfd_phase_sel in t ab le 18 reverses the polarity of the phase detector, to allow for negative slope v co o r inverting op-amp in the loop flter. pfd_up_en in t ab le 18 allows masking of the pfd up output, which effectively prevents the charge pump from pumping up. pfd_dn_en in t ab le 18 allows masking of the pfd down output, which effectively prevents the charge pump from pumping down. de-asserting both pfd_up_en and pfd_dn_en effectively tri-states the charge pump while leaving all other functions operating internally. pfd jitter and lock detect background i n normal phase locked operation the divided v co signal arrives at the phase detector in phase with the divided crystal signal, known as the pfd reference signal. despite the fact that the device is in lock, the phase of the v co s ignal and the pfd reference signal vary in time due to the phase noise of the reference and v co oscillators, the loop bandwidth used and the presence of fractional modulation or not. t he total integrated noise from the v co normally dominates the variations in the two arrival times at the phase detector in integer mode. i f w e wish to detect if the v co is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. t he standard deviation of the arrival time of the v co signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked v co has a constant phase noise, 2 (? 0 ), at offsets less than the loop 3 db bandwidth and a 20 db per decade rolloff at greater offsets. t he simple locked v co phase noise approximation is shown in figure 10. figure 10. synthesizer phase noise & jitter 2 (? 0 ) 2 (? 0 ) r 2 /hz ? 0 b information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 9 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll pfd jitter and lock detect background (continued) with this simplifcation the total integrated v co p hase noise, f 2 , in rads 2 at the phase detector is given by where b is the 3 db corner frequency of the closed loop pll n i s the division ratio of the prescaler since the simple integral of (eq 1) is just a product of constants, we can easily do the integral in the log domain. for example if the v co phase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio is 100, then the integrated phase noise at the phase detector, in db, is given by: f 2 db = 10log ( f 2 (? 0 ) b/n 2 ) = -100 +50 +5 -40 = 85dbrads 2 or equivalently, f = 10 -85/20 = 56.2 urads = 3.22 milli-degrees rms. while the phase noise reduces by a factor of 20log n after division to the reference, due to the increased period of the pfd reference signal, the jitter is constant. t he r ms jitter from the phase noise is then given by t jpn = t pfd f /2 i n th is example if the pfd reference was 50mhz, t pfd = 20nsec, and hence t jpn = 0.179 psec. a n ormal 3 sigma peak-to-peak variation in the arrival time therefore would be 3 t jpn = 0.759 psec. i f t he synthesizer was in fractional mode, the fractional modulation of the v co divider will dominate the jitter. t he e xact standard deviation of the divided v co signal will vary based upon the modulator type chosen, however a typical modulator will vary by about 3 division ratios, 4 division ratios, worst case. i f, for example a nominal v co at 5 ghz is divided by 100 to equal the pfd reference at 50 mhz, then the worst case division ratios will vary by 100 4. hence the peak variation in the arrival times caused by ? modulation of the fractional synthesizer at the reference will be i f we n ote that the distribution of the delta sigma modulation is approximately gaussian, we could approximate t j?pk as a 3 sigma jitter, and hence we could estimate the rms jitter of the ? modulator as about 1/3 of t j?pk or about 266 psec in this example. hence the total rms jitter t j , expected from the delta sigma modulation plus the phase noise of the v co wo uld be given by the rms sum, where i n th is example the jitter contribution of the phase noise calculated previously would add only 0.18psec more jitter at the reference, hence we see that the jitter at the phase detector is totally dominated by the fractional modulation. hence, we have to expect about 800 psec of normal variation in the phase detector arrival times when in fractional mode. i n a ddition, lower v co frequencies with high pfd reference frequencies will have much larger variations. for example a 1ghz v co operating at near the minimum nominal divider ratio of 36, would according to (eq 2) exhibit about 4 nsec of peak variation at the phase detector, under normal operation. (eq 1) (eq 2) (eq 3) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 10 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll pfd jitter and lock detect background (continued) i n s ummary, the lock detect circuit must not interpret fractional modulation or normal phase noise related jitter as being out of lock, while at the same time declaring loss of lock when truly out of lock. pfd lock detect lkd_enable in t ab le 14 enables the lock detect functions of the hm c 70 0lp4(e). t he lock detect circuit in the hm c 70 0lp4(e) places a one shot window around the reference. t he one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator. c le aring ringosc_oneshot_sel ( t ab le 14 ) will result in a fxed analog based nominal 10 nsec window, as shown in figure 11. setting ringosc_oneshot_sel will result in a variable length widow based upon a high frequency internal ring oscillator. t he ring oscillator frequency is controlled by ringosc_cfg . t he resulting lock detect window period is then generated by the number of ring oscillator periods defned in oneshot_duration , both in ( t ab le 14 ). wincnt_max in t ab le 14 defnes the number of consecutive counts of the divided v co that must land inside the lock detect window to declare lock. i f f or example we set wincnt_max = 1000 , then the v co arrival would have to occur inside the 10 nsec widow 1000 times in a row to be declared locked, which results in a lock detect flag high. a single occurrence outside of the window will result in an out of lock, i.e. lock detect flag low. o nc e low, the lock detect flag will stay low until the wincnt_max =1000 condition is met again. t he lock detect flag is output to ld_sd o pin according to pfd_ld_open ( t ab le 18 ) or to the internal sp i read only register if locked = 1 ( t ab le 21 ). setting pfd_ld_open will display the lock detect flag on ld_sd o except when a serial port read is requested, in which case the pin reverts temporarily to the serial data o ut pin, and returns to the lock detect flag after the read is completed. t im ing of the lock detect and serial data o ut functions are shown in figure 11. figure 11. normal lock detect window when operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in integer mode. t he phase detector linearity is worse when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the pfd reference and the v co at the phase detector. i n s uch a case, for example with an offset delay, as shown in figure 12 , the v co arrival will always occur after the reference. t he l ock detect circuit can accommodate a fxed offset delay by setting lkd_win_asym_enable and win_asym_up_sel in t ab le 14 . similarly the offset can be in advance of the reference by clearing lkd_win_asym_up_sel while leaving lkd_win_asym_enable set both in t ab le 14 . t he re are certain conditions, such as operating near the supply limits of the charge pump which make it advantageous to use advanced or delayed phase offset, hence both are available. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 11 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll pfd lock detect (continued) figure 12. delayed lock detect window cycle slip prevention (csp) when the v co is not yet locked to the reference, the instantaneous frequencies of the two paths are different, and the phase difference of the two paths at the pfd varies rapidly over a range much greater than 2 radians. since the gain of the pfd varies linearly with phase up to 2, the gain of a conventional pfd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. t he charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. t hi s can make the v co frequency actually reverse temporarily during locking. t hi s phenomena is known as cycle slipping. c yc le slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in figure 13, and increases the time to lock to a value far greater than that predicted by normal small signal laplace analysis. t he hm c 70 0lp4(e) pfd features an ability to virtually eliminate cycle slipping during acquisition. when enabled, the c yc le slip prevention ( c sp ) feature essentially holds the pfd gain at maximum until such time as the frequency difference is near zero. c yc le slip prevention, allows faster lock times as shown in figure 13. t he use of the cycle slip feature is enabled with csp_enable (see t ab le 14 ) . t he c yc le slip prevention feature may be optimized for a given set of pll dynamics by adjusting the pfd sensitivity to cycle slipping. t hi s is achieved by adjusting csp_corr_magn in t ab le 13 . figure 13. cycle slip prevention (csp) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 12 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll charge pump gain a simplifed diagram of the charge pump is shown in figure 14. c ha rge pump up and down gains are set by cp_upcurrent_sel and cpdncurrent_sel respectively ( t ab le 16 ). each of the up and d n charge pumps consist of two 500u a current sources and one 1000u a current source. t he current gain of the pump in radians/ a mp is equal to the gain setting of this register divided by 2. for example if both cp_upcurrent_sel and cpdncurrent_sel are set to 010 the output current of each pump will be 1m a a nd the phase detector gain kp = 1m a /2 radians, or 159u a /r ad. charge pump gain trim each of the up and d n pumps may be trimmed to more precise values to improve current source matching or to allow fner control of pump gain. t he pump trim controls are 4bits, binary weighted for up and d n , i n cp_uptrim_sel and cp_dntrim_sel respectively ( t ab le 16 ). lsb weight is 7 a , ma ximum trim is 105 a . charge pump phase offset i deally the phase detector operates with zero offset, that is, the divided reference signal and the divided v co signal arrive at the phase detector inputs at exactly the same time. i n s ome modes of operation, such as fractional mode, charge pump linearity and ultimately, phase noise, is better if the v co and reference inputs are operated with a phase offset. n or mally integer mode of operation is best with no phase offset. a phase offset is implemented by adding a constant d c leakage to one of the charge pumps. d c leakage may be added to the up or d n pumps using chp_ upoffset_sel or chp_dnoffset_sel . t he se are 3 bit registers with 55 a l sb. maximum offset is 385u a . fo r best spectral performance in fractional mode the leakage current should be programmed to: r eq uired leakage c ur rent (u a ) = (4 e-9 + 4x t vc o) x fcomparison (hz) x c p cu rrent (u a ) charge pump operation near the rail i t should be noted that the charge pump is a non-ideal device. phase locked operation with the tuning voltage very n ear the positive charge pump supply voltage or very near ground will degrade the phase noise performance of the synthesizer. exactly how close to the supply limits that one should operate is a question of margin needed for the application in question and user judgement. figure 3 . gives some idea of the typical performance near the supply limits. i t s hould be noted that if operation is necessary very near the supply limits, for example less than 500mv from the supply limit, then it is recommended to operate with a d c leakage that leaks in the direction of the supply. for example, if the charge pump supply is 5.5v and locked operation is required with a v co tune voltage of 5.2v, then operating with up leakage on the charge pump will improve operation in this region. similarly if phase locked operation is needed, with a v co t une voltage of say 300mv, then operating with d n l eakage is recommended. a s a n example, if the main pump gain was set at 1m a , a n offset of 385u a would represent a phase offset of about (385/1000)*360 = 138degrees. n or mally it is sufficient to offset the pump by just slightly larger than the delta sigma excursions for best phase noise. best spurious operation usually occurs with d n offset with non-inverting loop flters and up offset with inverting loop flters. figure 14. charge pump gain & offset control information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 13 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll fractional mode fractional frequency tuning t he hm c 700lp4(e) synthesizer in fractional mode can achieve frequencies at fractional multiples of the reference. t he o utput frequency of the synthesizer is given by where n int is the integer division ratio, an integer number between 36 and 65,567 (see intg t ab le 10) n frac is the fractional part, a number from 1 to 2 24 see frac t ab le 11 r is the reference path division ratio, see rdiv t ab le 9 ? xtal is the frequency of the reference oscillator input ? pfd is the pfd operating frequency ? xtal / r a s an e xample ? xtal = 50 mhz r = 1 ? pfd = 50 mhz n int = 45 n frac = 1 i n this example the output frequency of 2,300,000,002.98 hz is achieved by programming the 10 bit binary value of 4 6d =2eh = 0000 0000 0010 1110 into intg in t ab le 13. similarly the 24 bit binary value of the fractional word is written into frac in t ab le 11 , 16,777,215d = fff fffh = 1111 1111 1111 1111 1111 1111 1d = 000 001h = 0000 0000 0000 0000 0000 0001 example 2: set the output to 4.600 025 ghz using a 100 mhz reference, r =2 . find the nearest integer value, n int , n int = 92, f int = 4.600 000 ghz t hi s leaves the fractional part to be ? frac =25 khz since n frac must be an integer number, the actual fractional frequency will be 4,600,025,001.17hz, an error of 1.17hz or 0.00025ppm. here we program the 16 bit n in t = 92d = 5 c h = 00 00 0000 0101 1100 and t he 2 4 bit n fra c = 8389d = 20 c 5h = 0 000 0010 0000 1100 0101 i n a ddition to the above frequency programming words, the fractional mode must be enabled by setting frac_rstb and buff_rstb t ab le 13 . o th er dsm confguration registers should be set to the recommended register values. (eq 4) (eq 5) (eq 6) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 14 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll fsk modulation t he hm c 700lp4(e) is capable of a simple binary frequency shift keying (fsk) modulation. t he internal modulation is unshaped fsk. t he loop bandwidth of the synthesizer must be fxed by the user to achieve symbol shaping as required. when the fsk mode of operation is enabled, via fsk_enable ( t ab le 13 ), and se n is held low, the synthesizer will output binary fsk frequency hops in response to data input on the sd i pin. when se n is set, the fsk modulation will stop and return to f 0 . s c k must not be toggled when transmitting data in fsk mode. f sk modulation is normally defned by a deviation, ? , and a modulation rate, ? m . t he deviation is defned as the d ifference between the frequency transmitted when input data is 0, ? 0 , and the frequency transmitted when the input data is 1, ? 1 . ? o is the frequency programmed in the frequency registers as was defned in (eq 4), that is: ? 1 is the fractional frequency achieved by adding the value in the seed register to the value in the frac register, that is: where n int is the integer division ratio, an integer number between 36 and 65,567 (see integer r egister) n frac is the fractional part, a number from 1 to 2 24 n seed is the seed part, a number from 1 to 2 24 r is t he reference path division ratio ? ref is the frequency of the external reference input i n th is case the deviation f is given simply by fsk data bits on sd i will be latched into the synthesizer on the falling edge of the divided reference rate, ? pfd . i f for e xample r =1 , and ? ref = 50 mhz, the input fsk data would be oversampled every 20nsec on the falling edge of the input reference. t he ? m rate of the fsk data is simply the inverse of twice the period of the data bits. for example, if the data bit period is 1msec the fm rate is 500 hz. i f a n unshaped binary fsk is desired, the closed loop bandwidth of the synthesizer should be larger than the ? m rate by a sufficient margin. for practical fsk transmissions the ? m rate is limited by the radio link budget, channel spectral emission restrictions and practical closed loop bandwidths of the fractional synthesizer. (eq 7) (eq 8) (eq 9) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 15 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll integer mode t he hm c 70 0lp4(e) synthesizer is capable of operating in integer mode. i n i nteger mode the synthesizer step size is fxed to that of the pfd frequency, f pfd . i nteger mode typically has the lower phase noise for a given pfd o perating frequency, than fractional mode. t he advantage is usually of the order of 4 to 6 db. i nt eger mode, how- ever, often requires a lower pfd frequency to meet step size requirements. t he fractional mode advantage is that higher pfd frequencies can be used, hence lower phase noise can often be realized in fractional mode. integer frequency tuning i n integer mode the digital ? m odulator is shut off and the division ratio of the prescaler is set at a fxed value. t o r un in integer mode clear frac_rstb and buffrstb t ab le 13 . t he n program the integer portion of the frequency as explained by (eq 4), ignoring the fractional part. vco divider register buffering t he v co divider registers inside the hm c 70 0lp4e are not double buffered. a s s oon as either the integer ( r eg 3) or fractional ( r eg 4) v co divider register is programmed the new value takes effect. under certain conditions, this can present a momentary mis-load of the internal v co divider which can take several milliseconds to clear. i n t ime sensitive frequency settling applications a specifc programming sequence is required to avoid this delay. t hi s delay arises only when the upper 11 bits of the 16 bit v co divider ( r eg 3) are all changing state such that none of the bits remain as a 1. i n ti me sensitive applications the following programming sequence should be used. for fractional mode: write r eg ister 5 = 0h (zero the seed); write r eg ister 4 = 0h (zero the fractional divide value); write r eg ister 3 to the intermediate integer divide value; write r eg ister 3 to the fnal integer divide value; write r eg ister 5 = 50894 c h (o r any other non-zero value); write r eg ister 4 to the fnal fractional divide value; for integer mode: write r eg ister 3 to the intermediate integer divide value; write r eg ister 3 to the fnal integer divide value; t he intermediate v co divider register value ( r eg ister 3) must have a 1 in the upper 11 bits (lower 5 bits do not matter) that does not change when going from the starting value to the intermediate value and then from the intermediate value to the fnal value. a simple algorithm to calculate a suitable interim value is to or t he r eg ister 3 start value with the r eg ister 3 final value. for example, if you are going from 74h to 80h the or e d value would be f4h. t hi s behaviour is not present on other hittite microwave pll devices. soft reset and power on reset t he hm c 700lp4(e) features a hardware power on r es et (p or ). a ll chip registers will be reset to default states approximately 250us after power up. t he sp i registers may also be soft reset by an sp i write to strobe register rst_swrst ( t ab le 7 ) power down mode c hip power down is done by deasserting c hi p enable, c e, pin 23 (low = disabled). t hi s will result in all analog functions and internal clocks disabled. c ur rent consumption will typically drop below 10 a in power down state. during power down, the serial register writes will still operate, however, serial data output is disabled so r ea d operations will not work. i t i s possible to control power down mode from the serial port register rst_chipen_from_spi by clearing rst_chipen_ pin_select ( t ab le 8 ). information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 16 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll i t is also possible to leave various blocks on when in power down (see t ab le 8 ), including: a. digital c lo cks b. i nt ernal bias reference sources c. pfd block d. c ha rge pump block e. r ef erence path buffer f. v co p ath buffer g. digital i / o t es t pads chip identifcation t he version of the synthesizer is described in t able 6 . version information may be read from the synthesizer by reading the content of chip_id in r eg 0 0h. serial port t ypical serial port operation can be run with s c k at s peeds up to 50mhz. serial port write operation table 4. timing characteristics parameter c on ditions min t yp max units t 1 se n t o s c k se tup t im e 8 nsec t 2 sd i t o s c k se tup t im e 5 nsec t 3 sd i t o s c k se tup t im e 5 nsec tsck s c k pe riod 20 nsec t 4 s c k high duration 8 n sec t 5 s c k low duration 8 n sec t 6 se n h igh duration 640 nsec t 7 se n l ow duration 20 nsec a typical w rit e cy cle is shown in figure 15. a. t he master (host) both asserts se n (serial port enable) and clears sd i to indicate a w ri t e c ycle, followed by a rising edge of s c k. b . t he slave (synthesizer) reads sd i on the 1st rising edge of s c k af ter se n . s d i low initiates the write cycle (/w r ). c . ho st places the six address bits on the next six falling edges of s c k, m sb frst. d. sl ave registers the address bits in the next six rising edges of s c k (2 -7). e. ho st places the 24 data bits on the next 24 falling edges of s c k, m sb frst . f. sl ave registers the data bits on the next 24 rising edges of s c k (8 -31). g. se n i s de-asserted on the 32nd falling edge of s c k. h . t he 3 2 nd falling edge of s c k co mpletes the cycle. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 17 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll figure 15. serial port timing diagram - write serial port write operation serial port read operation a typical r e a d cy cle is shown in figure 16. a. t he master (host) asserts both se n (serial port enable) and sd i to indicate a r e a d c ycle, followed by a rising edge s c k. n ot e: t he lock detect function is multiplexed onto the ld_sd o pin. i t i s suggested that lock detect (ld) only be considered valid when se n is low. i n f act ld will not toggle until the frst active data bit toggles on ld_sd o , a nd will be restored immediately after the trailing edge of the lsb of serial data out as shown in figure 15. b. t he slave (synthesizer) reads sd i on the 1st rising edge of s c k af ter se n . s d i high initiates the r e a d cy cle ( r d) . c. ho st places the six address bits on the next six falling edges of s c k, m sb frst. d. sl ave registers the address bits on the next six rising edges of s c k (2 -7). e. sl ave switches from lock detect and places the requested 24 data bits on sd_ld o on the next 24 rising edges of s c k (8 -31), msb frst . f. ho st registers the data bits on the next 24 falling edges of s c k (8 -31). g. sl ave restores lock detect on the 32nd rising edge of s c k. h . se n i s de-asserted on the 32nd falling edge of s c k. i . t he 3 2nd falling edge of s c k co mpletes the r e a d cy cle. figure 16. serial port timing diagram - read serial port operation information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 18 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll general purpose output (gpo) pins t he hm c 70 0lp4(e) also supports a simple two pin gp o bus implemented on pins d1 and d0. gp o operation requires that gp o output pads be enabled via gpio_pads_en ( t ab le 15 ). t wo b it arbitrary data may be written to the gp o outputs via register gpo_test , when gpo_select is frst set to 10d ( t ab le 20 ). o th er test waveforms, described in t ab le 20, may be output to the gp o pins according to the value written to gpo_select . i f t he gp o outputs are not used, and it is desirable that they are as quiet as possible then the gp o pads should be disabled via gpio_pads_en ( t ab le 15 ) and gpo_select set to a value that has a static source, such as 10d. register map note: for r ea d o pe rations from register 00h, it is r ea d o nl y containing the chip i d. c ur rent hittite synthesizer chip i ds a re shown in t ab le 6. table 6. reg00h id (read only) register bit n am e width default description [23:0] chip_ i d 24 4 78708h or 485901 part n um ber, description hm c 70 0lp4, 16-bit 5.5v for write operations to register 00h, it is a write o nl y strobe register as defned in t ab le 7. table 7. reg00h rst strobe register bit n am e width default description [0] rst_swrst 1 n/a strobe (w ri t e on ly ) generates soft reset. r es ets all digital and registers to default states. table 8. reg 01h rst register bit n am e width default description [0] rst_chipen_pin_select 1 1 1 = c hi p enable via c e p in, c e ( pin 23) enables chip. c e l ow puts chip in power down. 0 = c hi p enable via sp i ( rst_chipen_from_spi), c e pi n is ignored [1] rst_chipen_from_spi 1 0 1= c hi p enable when rst_chipen_pin_select = 0 0= power down when rst_chipen_pin_select = 0 see power down mode description and csp_enable r eg 07 <20> i f rs t_chipen_pin_select =1 this register is ignored [2] rst_chipen_digclks_keep_on 1 0 keeps digital clocks on when chip is power down from any source [3] rst_chipen_bias_keep_on 1 0 keeps chip internal bias generators on when chip is power down from any source [4] rst_chipen_pfd_keep_on 1 0 keeps internal pfd block on when chip is power down from any source [5] rst_chipen_chp_keep_on 1 0 keeps internal c harge pump block on when chip is power down from any source [ 6] rst_chipen_refbuf_keep_on 1 0 keeps reference path buffer on when chip is power down from any source [7] rst_chipen_vcobuf_keep_on 1 0 keeps v co path r f buffer on when chip is power down from any source [ 8] rst_chipen_dig_io_keep_on 1 0 keeps digital io pins on when chip is power down from any source? [ 9] rst_chipen_rdiv_fe_sync 1 0 t ri-states the pfd on the next falling edge of the ref clock and also puts the chip to sleep information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 19 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 9. reg 02h refdiv register bit n am e width default description [13:0] rdiv 14 1 r eference divider r value (eq 4) 0 0h - illegal 01h - divide-by-1 (bypass) 10h - divide-by-2 11h - divide-by-3 etc ... 3fffh - divide-by-16, 383 t he r eference divider is controlled by several bits in register 8. see register 8 description for details. table 10. reg 03h frequency register - integer part bit n am e width default description [15:0] intg 16 c 8h v co d ivider i nt eger part, used in all modes, see (eq 4) fractional mode min 36d max 2?16 -1 = 65,535d integer mode min 32d max 2?16+31 = 65,567d table 11. reg 04h frequency - fractional part register bit n am e width default description [23:0] frac 24 0 v co d ivider fractional part (24 bit unsigned) see section fractional frequency t un ing used in fractional mode only min 0d max 2^24-1 table 12. reg 05h sd seed register bit n am e width default description [23:0] seed 24 0 fractional mode : seeds fractional modulator fsk mode : sets f1 in fsk mode when fsk_enable=1 (see section fsk modulation) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 20 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 13. reg 06h sd cfg register bit n am e width default description [7:0] reserved 87h [9:8] order 2 2h select the modulator t yp e 0 - not used 1 - not used 2 - t yp e b 3 - t yp e a [1 0] frac_rstb 1 1 0 holds the frac core in reset reset is used for integer mode or integer mode with c sp [ 11] buff_rstb 1 1 0 holds the frac core buffers in reset reset is used with frac_rstb=0 for integer mode, no c sp [ 12] bypass_mode 1 0 1 fractional modulator output is ignored, but fractional modulator continues to be clocked, used to test the isolation of the digital fractional modulator from the v co o utput in integer mode [13] autoseed_mode 1 1 loads the seed whenever the frac register is written [14] reserved 1 0 must be kept at 0 [15] fsk_enable 1 0 enables the fsk mode of operation and fsk input on sd i pi n, (see section fsk modulation) [16] reserved 1 0 [17] clkrq_refdiv_sel 1 0 selects the sd clock source 1 = reference divider clock 0 = v co d ivider clock (recommended) [18] clkrq_invert_clk 1 1 inverts the selected sd clock [19] sd_spare_out 1 0 spare [23:20] csp_corr_magn 4 8h c sp m agnitude correction (see section c yc le slip prevention ( c sp )) 0000 low magnitude 1111 high magnitude sign of the correction is determined automatically by the c sp s tate machine n ote: t o enable frac mode: s et r eg 6 [ 12:10]= 011 a ls o, r eg 9 [9:7] or r eg 9 [4:2] must be adjusted to mitigate spurs in frac mode (dn or up leakage) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 21 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 14. reg 07h lkd/csp register bit n am e width default description [9:0] wincnt_max 10 250 lock detect window sets the number of consecutive counts of divided v co that must land inside the lock detect window to declare l oc k [1 0] lkd_enable 1 1 enables internal lock detect function, n ot e output to lock detect flag on ld_ sdo as per figure 13 controlled by pfd_ld_open , reg 0bh pfd r eg ister [11] lkd_winasym_enable 1 0 asymmetrical window enables lock detect window to only lag or only lead the divided reference signal at the pfd, see figure 9 [12] lkd_win_asym_up_sel 1 0 1 selects lead window when lkd_winasym_enable=1 0 selects lag window when lkd_winasym_enable=1 [13] ringosc_oneshot_sel 1 0 1 ring osc based one shot for lock detection mode 0 nominal 20nsec analog one shot for lock detection mode [16:14] oneshot_duration 3 0 duration of the ringosc based oneshot pulse in lock detection mode [18:17] ringosc_cfg 2 0 lock detect ringosc frequency trim 00 fastest 11 slowest [19] ringosc_mode 1 0 force ringosc o n [2 0] csp_enable 1 1 cycle slip prevention ( c sp ) enable see section pfd lock detect for more information about this register. table 15. reg 08h analog en register bit n am e width default description [0] bias_en 1 1 enables main chip bias reference [1] cp_en 1 1 charge pump enable [2] pfd_en 1 1 pfd enable [3] refbuf_en 1 reference path buffer enable. set to 1 for normal operation. [4] vcobuf_en 1 1 vco path r f bu ffer enable [5] gpio_pads_en 1 1 gpio pads enable, pins d0 and d1 required for use of gp o p ort or v co s erial port [6] sdo_pad_en 1 1 ld_sd o p ad driver enable (pin 5) required for use of lock detect, serial port r ea d o pe ration or v co s erial port operation [7] vcodiv_digclk_en 1 1 vco divider output clk to digital enable [8] vcodiv_en 1 1 enable vco divider [9] reserved 1 0 [10] vcodiv_dutycyc_mode 1 0 vcodiv duty cycle mode stretches the v co d ivider output when n >3 2 [11] reserved 1 0 set to 0 for normal operation [12] rdiv_ref_to_dig_en 1 1 reference input applied to digital when set to 1, non-divided reference signal is fed to digital (required for normal operation) [13] rdiv_refdiv_to_dig_en 1 1 reference divider applied to digital, when set to 1, divided reference signal is fed to digital (required for normal operation) c harge pump control register. see figure 14 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 22 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 16. reg 09h cp register bit n am e width default description [1:0] r es erved set them to 0 2 0 [4:2] cp_upoffset_sel 3 0 c ha rge pump up o ff set c on trol 55u a /s tep 000 = 0u a 00 1 = 55u a 01 0 = 110u a .. . 111 = 385u a [6 :5] r es erved set them to 0 2 0 [9:7] cp_d n of fset_sel 3 0 c ha rge pump d n o ff set c on trol 55u a /s tep 000 = 0u a 00 1 = 55u a 01 0 = 110u a .. . 111 = 385u a [1 3:10] cfg cp_uptrim_sel 4 0 c ha rge pump up c ur rent t ri m 7u a /s tep 0000 = 0u a 00 01 = 7u a 00 10 = 14u a 01 00 = 28u a 10 00 = 56u a 11 11 = 105u a [1 7:14] cp_d n tr im_sel 4 0 c ha rge pump d n c ur rent t ri m 7u a /s tep 0000 = 0u a 00 01 = 7u a 00 10 = 14u a 01 00 = 28u a 10 00 = 56u a 11 11 = 105u a [2 0:18] cp_upcurrent_sel 3 0 c ha rge pump up m ai n c ur rent c on trol 500u a s tep 000 tristate if pfd also disabled 001 500u a 01 0 1000u a 01 1 1500u a 10 0 2000u a 10 1 2000u a 11 0 2000u a 11 1 2000u a [2 3:21] cp_d n cu rrent_sel 3 0 c ha rge pump up m ai n c ur rent c on trol 500u a s tep 000 tristate if pfd also disabled 001 500u a 01 0 1000u a 01 1 1500u a 10 0 2000u a 10 1 2000u a 11 0 2000u a 11 1 2000u a information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 23 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 17. reg 0ah cp op amp register bit n am e width default description [1:0] cp_opamp_bias_sel 2 0 c ha rge pump i nt ernal o p- a mp b ias select 00 - 540 a 01 - 6 89 a 10 - 9 43 a 11 - 1 503 a en abled with c hg p ump enable n ot e: this circuit affects internal charge pump operation and linearity. default setting is recommended. enabled with r eg 08h[1] cp_en table 18. reg 0bh pfd register bit n am e width default description [2:0] pfd_del_sel 3 0 sets pfd reset path delay. r ec ommended value 010 when in i nt eger mode, r eg b bits [2:0] should not be 000 because it doesnt ensure sufficient on time for the c p a t 50mhz. t hi s isnt an issue in fractional mode; [3] pfd_phase_sel 1 0 swaps the pfd inputs 1 negative v co t uning slope 0 positive v co t uning slope [4] pfd_up_en 1 1 enables the pfd up output according to state of pfd_mute_when_locked_enable, see reg0b<9> [5] pfd_dn_en 1 1 enables the pfd d n o utput according to state of pfd_mute_when_locked_enable, see reg0b<9> [6] pfd_ld_open 1 1 pfd lock detect o ut put enable, enables lock detect fag output to ld_sd o p in [7] pfd_pullup_ctrl 1 0 forces pfd up output on [8] pfd_puldn_ctrl 1 0 forces pfd d n o utput on [9] pfd_mute_when_locked_ enable 1 0 1: if set: when locked disables up if pfd_up_en=0 when locked disables d n i f pfd_dn_en=0 when no t locked, allows both up and d n to be active and ignores pdf_up_en and pfd_dn_en 0: if clear, pfd_dn_en and pfd_up_en enable up and d n ou tputs at all times [10] spare0 1 0 reserved [11] spare1 1 1 reserved table 19. reg 0ch vco spi register bit n am e width default description [9:0] vcospi_vco_data 10 0 data register contents, when written automatically outputs this data via v co s p i w hen to_gpo_sdo=1 reg09<7> information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 24 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll table 20. reg 0dh gpo_spi_rdiv register bit n am e width default description [3:0] gpo_select 4 10d t est signals selected here are output to gpo pins when g po_pads_en=1 ( t ab le 15 ) d1 & d0 0: clk_vcodiv & clk_refdiv 1: pfd_up & pfd_dn 2: ref o ut & r efdiv o ut 3 : seed_stb_sypulse_test & frac_stb_sypulse_test 4: intg_inbuff_enable_test & clk_sd 5: oneshot_trigg_test & oneshot_pulse_test 6: 0 & ringosc_test 7: csp_corr_add & csp_corr_sub 8: pfd_sat_refdiv & pfd_sat_vcodiv 9: (csp_corr_add or csp_corr_sub) & pfd_sat_rstb 10: gpo_test , see r eg 0d<5:4> 11: not used 12: not used 13: not used 14: not used 15: not used [5:4] gpo_test 2 0 data written to this register is output to d0 and d1 pins when gpo_select = 10d [6] refclkdiv4 1 0 1: sel ref divby4 for clocking the vco_spi 0: sel ref divby1 for clocking the vco_spi [7] to_gpo_sdo 1 0 enable the automatic output of vcospi_vco_data to ld_sd o o ut put v co _s p i c lock to d1 (see reg0d<6> ) o ut put v co _s p i e n t o d0 table 21. reg 0fh ld state register (read only) bit n am e width default description [0] locked 1 0 r ea d only lock detect fag, 1 when locked information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 25 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com pll - fractiona l - n - s m t 0 0 - 26 HMC700LP4 / 700lp4e v11.0411 8 ghz 16-bit fractional-n pll outline drawing part n umber p ackage body material lead finish msl r at ing package marking [3] hm c 700lp4 l ow stress i nj ection molded plastic sn/pb solder msl1 [1] h700 xxxx hm c 70 0lp4(e) r oh s-compliant low stress i nj ection molded plastic 100% matte sn msl1 [2] h700 xxxx [1] max peak refow temperature of 235 c [2 ] max peak refow temperature of 260 c [3 ] 4-digit lot number xxxx package information not es: 1 . le a df ra me m at e ri a l: c o pp e r a ll o y 2. d i me n s io n s a r e i n i nc he s [m i ll i me t e r s] . 3. le a d sp ac in g to le ra nc e i s n on - c um ul at i ve 4 . p a d bu rr l e n g t h sh a ll b e 0.15mm m a x i mu m. p a d bu rr h e i gh t s h a ll b e 0.05mm m a x i mu m. 5. p ac k a ge w ar p sh a ll n ot e x c ee d 0.05mm. 6. a ll g ro u n d le a ds a n d g ro u n d p a dd le mus t b e s o ld e r ed to p c b r f g ro u n d. 7 . r ef e r to h it tit e a pp l ic ation n ot e f or s ugges t ed p c b l an d p at t e rn . evaluation pcb please reference hm c 70 0lp4 product n ot e for information on evaluation p c b ki t and list of materials. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se, no r for any infring emen ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an alog .com app li cation sup po rt: p ho ne: 1-800-analog-d

▲Up To Search▲

Price & Availability of HMC700LP4

	To Download HMC700LP4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .